Integrated circuit chips, or electronic devices, are generally packaged as discrete devices as one chip per package or as part of a multi-chip hybrid circuit, or hybrid package, where a plurality of integrated circuit chips are mounted in one such package. Each hybrid package may be treated as a building block for complex electronic circuits and systems such as a general purpose digital data processing system.
A substantial part of the cost to manufacture computer systems is directly dependent upon the space occupied by the integrated circuit chips used to fabricate the systems.
Increasingly higher packaging density is required for higher performance systems to minimize signal propagation delays between chips and to improve electrical performance through reduced inductance interconnections both of which can be achieved by reducing the length of conduction paths which interconnect the chips.
Typically, an integrated circuit chip has a back face and an active face with an array of I/O terminals on the active face. The terminals are electrically connected to the circuits within the integrated circuit chip.
A commonly used arrangement for increasing chip packaging density is the mounting of a number of chips side by side on a packaging substrate with either the active or back face placed facing the substrate. The packaging substrate is typically a ceramic containing conductor patterns therein or a polymeric printed circuit board.
The packaging substrate contains conductor patterns to interconnect the chips electrically. Fabrication constraints place a limit on the minimum distance between chips. Therefore, the minimum chip-to-chip space determines the minimum conductor path interconnecting the chips and, to a major extent, the minimum propagation delay between the chips.
Another structure to increase the chip packaging density is formed by mounting or stacking one chip on top of another chip rather than placing chips side by side.
Prior art shows examples of stacking chips to form double-chip structures. In some cases, chips are contained within a rigid housing with the back of one chip facing the back of the second chip, there being a rigid support between the chips on which the back of each chip rests. The active faces are directed away from each other to permit easy electrical connection to the exposed input/output (I/O) terminals on each chip. U.S. Pat. No. 4,288,841 to Gogal and U.S. Pat. No. 4,423,468 to Gattoctal describe structures of this type wherein one end of a wire is bonded to a chip I/O pad and the other end of the wire is bonded to a contact pad within the rigid housing.
In another type of double-chip structure, the back of one chip is placed facing the active face of the second chip. Both chips are held in place by the package housing. Electrical connection is made to each chip separately by bonding one end of a wire to a contact pad on the chip and bonding the other end of the wire to pads within the housing or to ends of a lead frame which project outwardly from the housing. Examples of these types of structures are described in PCT patent application to Motorola, Inc. PCT/FR83/00214 (published May 9, 1985, Publication No. WO 85/02060) and in Japanese patent 56-62350 to Hitachi Seisakusho K. K.
In another type of double-chip structure, the active face of a chip is placed facing the active face of a second chip. This type of structure is shown in Japanese patent 56-24955 of Fujitsu K. K. The back of a first chip is mounted onto a first substrate. Wires are bonded between the chip I/O terminals and metal patterns on the substrate. A second combination of chip on substrate is formed. The two combinations are mounted together with the active face of the chips facing each other. The substrates are held together by rigid supports, there being a space between the active faces of each chip.
Another double-chip structure having the active faces of the chips facing each other is described in Japanese patent 56-137665 to Cho Lsi Gijustsu Kendyu Kumai which is a DIP type module containing therein two semiconductor chips having solder mounds on their active faces for electrical connection to the circuits within the chips. The active faces of the chips are mounted facing each other with the solder mounds on one chip aligned with respective solder mounds on the other chip. The inner ends of a plurality of beam leads are aligned with the aligned solder mounds on each chip and soldered between the solder mounds. The double-chip combination is enclosed within a thick polymer enclosure through which the beam leads project.
In an article entitled "NEC Lamination Method Bonds Chips Face To Face" in the J. Electronic Engineering, February 1985, p. 20 there is a brief description of a laminate process that puts two conventionally made chips face-to-face and bonds them under 300 degrees centigrade to 400 degrees centigrade and pressure to form a double layered, three-dimensional device which has a contact pad on one chip thermocompression bonded to a contact pad on the other chip. Polymide, prepared as a passivating layer on the active face of each chip, surrounds the contact pads and fills the space between the active faces of the chips. There are no leads projecting outwardly from between the chips.
U.S. Pat. Ser. No. 4,585,157 to Belcher describes a double-chip structure wherein the active face of one chip is placed facing the active face of a second larger chip. Beam leads electrically interconnect the chips and provide the means for external electrical connection to the double-chip structure. The structure is formed by first thermocompression bonding the inner ends of beam leads to contact pads on the active face of the smaller chip. The beam leads project outwardly away from the smaller chip periphery. The active face of the larger chip is placed facing the active face of the smaller chip. The part of the beam lead projecting beyond the smaller chip periphery is thermocompression bonded to contact pads on the larger chip, thereby electrically connecting a contact pad on the smaller chip to a contact pad on the larger chip. The outer end of the beam lead projects outwardly beyond the periphery of the larger chip.
An invention described herein is a double-chip structure having the chips face-to-face with beam leads solderlessly bonded between contact metallurgical patterns on each chip. Although it is commonly known to solderlessly bond beam leads to contact pads on a single chip, the prior art does not teach or suggest solderlessly bonding beam leads between contact pads of a double-chip structure. Quite surprisingly, it has been found that such a double-chip structure can be formed by aligning the contact pads on each chip with beam lead ends therebetween and pressing the chips together providing heat to the back of the chips to bond, simultaneously and solderlessly, the beam lead end to both contact pads.
The structure of the present invention is similar to that of Japanese patent 56-137665 described above. The difference being that in the structure of the present invention beam leads are solderlessly bonded between contact pad whereas in Japanese patent No. 56-137665, the beam leads are solder bonded between contact pads.
For a structure having beam leads solder bonded between contact pads, the alignment of the solderable contact pads on each chip with beam lead ends therebetween is substantially easier than the alignment of solderless contact pads with the beam leads therebetween. The solder bonded double-chip structure is formed by aligning the solder coated contact pads on the first and second chip with ILB ends of the beam leads pressed therebetween. The ILB ends have a solder wettable surface. The aligned chips and beam leads are heated to a temperature to reflow the solder. The reflowed solder beads up on the solder wettable surface because of surface tension at the molten solder surface. If there is misalignment between the contact pads and the beam leads, the surface tension of the molten solder tends to pull the solder coated pads and beam leads into alignment. It is only necessary that the molten solder mounds on each chip contact the beam lead end which has a solder wettable surface for this self alignment to occur. On the other hand, for a solderless bond of a beam lead end between contact pads on two chips, there is no self alignment mechanism. If there is enough misalignment between each contact pad and the beam lead therebetween, when the contact pads are pressed towards each other to compress the beam lead an effective and reliable solderless bond will not be formed.
A solderless bond, however, has substantial advantage over a solder bond. A solder bond is intrinsically weak and has a low melting point. During the operation of the devices of the double device structure, power is dissipated which can heat the structure from room temperature to as high as 120.degree. C. The devices are cycled many times between low and high temperature. This cycling generates stress in the solder mound causing it to deform which can result in a part of the solder mound slipping or sliding relative to the remainder of the mound causing a crack to form in the mound. Further, temperature cycling can cause the crack to propagate resulting in a failure of the electrical connection of the beam lead to the contact pad. On the other hand, a solderless bond is not subject to this type of deformation. In the solderless bond of the present invention, temperature cycling induced stresses result in elastic deformation of the contact pad and beam lead ends. The elastically deformed solderless bonds do not show the cracking degradation which occurs on the solder bond structure.
State of the art IC chips useful to practice the present invention can have as many as 400 I/O, each I/O having a 1 mil dimension with a 2 mil pitch. State of the art beam leads also have an ILB dimension as small as 1 mil with a 2 mil pitch. For a cost efficient high volume manufacture of the solderlessly bonded double-device structures of the present invention which have a high I/O count and small and closely spaced contact pads and beam lead ILB ends, the bonding must be done rapidly with a highly reliable interconnection of the beam leads to the contact pads.
Quite surprisingly, it has been found that the solderlessly bonded double-device structures of the present invention can be made with high manufacturing throughput and a solderless interconnection having high reliability.
It is therefore an object of this invention to provide an improved double-device structure wherein beam leads are solderlessly bonded between contact metallurgical patterns on each chip of a double-device structure wherein the leads project outwardly from between the two devices. Each device can be an IC chip or one device can be an IC chip and the other a device containing decoupling capacitors. The contact metallurgical patterns on the active faces of the devices in some applications are electrically connected to device I/O terminals, in other applications, as described hereinbelow, they are not.
In fabricating hybrid packages, an approach that lends itself to automating the process of mounting leads to a double-device structure is through the use of a manufacturing format known as tape automated bonding (TAB) tape. The TAB tape provides the beam leads which project outwardly from between the chips. The beam leads provide a means for externally electrically connecting the double-device structure to a substrate on which the double-device structure is mounted.
A TAB tape has a spaced series of sets of beam lead patterns. It is common in the art to use TAB tape in an automated process to bond a plurality of beam leads simultaneously to I/O terminals in a single chip active face. Each beam lead has an inner lead bond (ILB) site at one end and an outer lead bond (OLB) site at the other end. The inner lead bond sites are bonded to the chip I/O terminals.
In an invention described herein, ILB ends of a beam lead set are aligned respectively with contact metallurgical patterns on the first device. A second chip is placed facing the first chip active face. The I/O terminals or contact pads on the second chip are aligned respectively with ILB ends of the beam lead set of the TAB tape. The ILB end of the beam leads are bonded between the terminals or contact pads of the first and second chip. Therefore, a TAB tape is fabricated having two chips bonded to the beam leads of each beam lead set. The beam leads at each beam lead set project outwardly from between the two chips.
It is therefore another object of this invention to provide an improved tape automated bonding structure having a double-chip structure formed at each set of a spaced series of sets of beam lead patterns on a tape automated bonding tape.